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69 commits 4 branches 0 tags 910 KiB
  • Verilog 60.6%
  • C 29.9%
  • Assembly 6.3%
  • Makefile 2.9%
  • Python 0.3%
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Filename Latest commit message Latest commit date
Bastiaan van der Plaat 433ed4de25 Make taro font mem writable and so changeable
2026-08-28 17:14:16 +02:00
boot Make taro font mem writable and so changeable 2026-08-28 17:14:16 +02:00
fpga Make taro font mem writable and so changeable 2026-08-28 17:14:16 +02:00
tools Make taro font mem writable and so changeable 2026-08-28 17:14:16 +02:00
.clang-format Add riscv32i core and basic assembler 2026-04-17 18:38:36 +02:00
.gitignore Add riscv32i core and basic assembler 2026-04-17 18:38:36 +02:00
LICENSE Add riscv32i core and basic assembler 2026-04-17 18:38:36 +02:00
Makefile Make taro font mem writable and so changeable 2026-08-28 17:14:16 +02:00
README.md Write more about make tasks in README.md 2026-08-18 20:48:17 +02:00

README.md

Zaheer Computer Platform

A work-in-progress computer desktop GUI platform running on cheap FPGAs

Getting Started

  • Install OSS CAD Suite and add it to PATH.
  • Run commands from the repository root.

Make Commands

  • make or make build - build the FPGA bitstream at target/top.fs.
  • make test - run the assembler, UART, text-mode, timing, and TMDS tests.
  • make load - load the bitstream onto the FPGA until power-off.
  • make flash - write the bitstream to persistent FPGA flash.
  • make serial - open the configured serial port at 115200 baud.
  • make clean - remove generated files in target/.

License

Copyright © 2020-2026 Bastiaan van der Plaat

Licensed under the MIT license.